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__________________ general description the max1240/max1241 low-power, 12-bit analog-to- digital converters (adcs) are available in 8-pin pack- ages. the max1240 operates with a single +2.7v to +3.6v supply, and the max1241 operates with a single +2.7v to +5.25v supply. both devices feature a 7.5? successive-approximation adc, a fast track/hold (1.5?), an on-chip clock, and a high-speed, 3-wire ser- ial interface. power consumption is only 37mw (v dd = 3v) at the 73ksps maximum sampling speed. a 2? shutdown mode reduces power at slower throughput rates. the max1240 has an internal 2.5v reference, while the max1241 requires an external reference. the max1241 accepts signals from 0v to v ref , and the reference input range includes the positive supply rail. an exter- nal clock accesses data from the 3-wire interface, which connects directly to standard microcontroller i/o ports. the interface is compatible with spi, qspi, and microwire. excellent ac characteristics and very low power com- bined with ease of use and small package size make these converters ideal for remote-sensor and data- acquisition applications, or for other circuits with demanding power consumption and space require- ments. the max1240/max1241 are available in 8-pin pdip and so packages. applications battery-powered systems portable data logging isolated data acquisition process control instrumentation ________________________________ features ? single-supply operation: +2.7v to +3.6v (max1240) +2.7v to +5.25v (max1241) ? 12-bit resolution ? internal 2.5v reference (max1240) ? small footprint: 8-pin pdip/so packages ? low power: 3.7w (73ksps, max1240) 3mw (73ksps, max1241) 66w (1ksps, max1241) 5w (power-down mode) ? internal track/hold ? spi/qspi/microwire 3-wire serial interface ? internal clock max1240/max1241 +2.7v, low-power, 12-bit serial adcs in 8-pin so ________________________________________________________________ maxim integrated products 1 19-1155; rev 5; 8/10 spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. ordering information continued at end of data sheet. top view 1 2 3 4 8 7 6 5 sclk cs dout gnd ref shdn ain v dd pdip/so max1240 max1241 pin configuration ordering information evaluation kit available functional diagram 7 ain t/h dout 6 1 output shift register control logic int clock 12-bit sar 8 2 3 5 ref 4 shdn 2.5v reference (max1240 only) gnd sclk cs max1240 max1241 v dd * dice are specified at t a = +25?, dc parameters only. ** future product?ontact factory for availability. /v denotes an automotive qualified part. + denotes a lead(pb)-free/rohs-compliant package. part* temp range pin - pa c k a g e inl (lsb) max1240 acpa+ 0 c to +70 c 8 pdip 1/2 max1240bcpa+ 0 c to +70 c 8 pdip 1 max1240ccpa+ 0 c to +70 c 8 pdip 1 max1240acsa+ 0 c to +70 c 8 so 1/2 max1240bcsa+ 0 c to +70 c 8 so 1 max1240ccsa+ 0 c to +70 c 8 so 1 max1240cc/d 0 c to +70 c dice* 1 max1240aesa/v+** -40 c to +85 c 8 so 1/2 max1240besa/v+ -40 c to +85 c 8 so 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com.
max1240/max1241 +2.7v, low-power, 12-bit serial adcs in 8-pin so 2 _______________________________________________________________________________________ electrical characteristics (v dd = +2.7v to +3.6v (max1240); v dd = +2.7v to +5.25v (max1241); 73ksps, f s clk = 2.1mhz (50% duty cycle); max1240?.7? capacitor at ref pin, max1241?xternal reference; v ref = 2.500v applied to ref pin; t a = t min to t max ; unless otherwise noted.) v dd to gnd .............................................................-0.3v to +6v ain to gnd................................................-0.3v to (v dd + 0.3v) ref to gnd ...............................................-0.3v to (v dd + 0.3v) digital inputs to gnd...............................................-0.3v to +6v dout to gnd............................................-0.3v to (v dd + 0.3v) dout current ..................................................................?5ma continuous power dissipation (t a = +70?) plastic dip (derate 9.09mw/? above +70?) ...........727mw so (derate 5.88mw/? above +70?)........................471mw cerdip (derate 8.00mw/? above +70?)................640mw operating temperature ranges max1240_c_a/max1241_c_a .........................0? to +70? max1240_e_ a/max1241_e_ a .....................-40? to +85? max1240_mja/max1241_mja ...................-55? to +125? storage temperature range............................-60? to +150? lead temperature (soldering, 10s) ................................+300? soldering temperature (reflow) pdip, so .....................................................................+260? cdip ...........................................................................+250? absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 71.5 max124_c input voltage range 0v ref v input capacitance aperture jitter <50 ps 16 pf max124_a max124_b/c aperture delay t apr 30 ns figure 8 track/hold acquisition time t acq 1.5 ? throughput rate 73 ksps f sclk = 2.1mhz conversion time parameter symbol min typ max units ?.5 ?.0 offset error lsb differential nonlinearity dnl ? lsb ?.0 gain temperature coefficient ?.5 ?.0 gain error (note 3) lsb ?.5 ?.0 resolution 12 bits relative accuracy (note 2) inl ?.5 lsb t conv 5.5 7.5 ? small-signal bandwidth signal-to-noise plus distortion ratio sinad 70 db 2.25 mhz full-power bandwidth total harmonic distortion thd -80 db 1.0 -3db rolloff mhz conditions spurious-free dynamic range ppm/? no missing codes over temperature max124_b/c ?.25 sfdr max124_a/b 80 up to the 5th harmonic db max124_a/b max124_a max124_a/b max124_c -88 max124_c 88 analog input conversion rate dynamic specifications (10khz sine-wave input, 0v to 2.500vp-p, 73ksps, f sclk = 2.1mhz) dc accuracy (note 1)
ppm/? max1240/max1241 +2.7v, low-power, 12-bit serial adcs in 8-pin so _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +2.7v to +3.6v (max1240); v dd = +2.7v to +5.25v (max1241); 73ksps, f s clk = 2.1mhz (50% duty cycle); max1240?.7? capacitor at ref pin, max1241?xternal reference; v ref = 2.500v applied to ref pin; t a = t min to t max ; unless otherwise noted.) v in = 0v or v dd ? t a = +25? ? 100 150 ?.01 ? i in sclk, cs input leakage v 0.2 input current conditions v shdn = 0v ? ?.01 10 v hyst sclk, cs input hysteresis v shdn = 0v or v dd ? ref input current in shutdown k 18 25 ?.0 shdn input current input resistance v 0.4 v sl shdn input low voltage v (note 5) v dd - 0.4 v sh shdn input high voltage pf 15 c in v ref output voltage sclk, cs input capacitance shdn = unconnected na shdn = unconnected ?00 shdn max allowed leakage, mid input v v dd /2 v flt shdn voltage, unconnected v 1.1 v dd - 1.1 v sm shdn input mid voltage i sink = 5ma units min typ max symbol parameter v 0.4 v ol output voltage low cs = v dd (note 5) pf 15 c out three-state output capacitance cs = v dd ? i source = 0.5ma ?.01 ?0 i l three-state leakage current v v dd - 0.5 v oh v v dd 3.6v 0.8 v il ? 0.1 capacitive bypass at ref sclk, cs input low voltage v 2.0 v ih sclk, cs input high voltage output voltage high i sink = 16ma v dd > 3.6v (max1241) 0.8 3.0 2.480 2.500 2.520 v input voltage range 1.00 v dd + 50mv max1240ac/bc ppm/? ref temperature coefficient ?0 50 ref short-circuit current 30 max1240ae/be ?0 60 max1240am/bm ?0 80 0ma to 0.2ma output load load regulation (note 4) 0.35 ma ? capacitive bypass at ref 4.7 max1240c ?0 digital output: dout digital inputs: sclk, c c s s , s s h h d d n n external reference (v ref = 2.500v) internal reference (max1240 only)
v dd = 3.6v max1240/max1241 +2.7v, low-power, 12-bit serial adcs in 8-pin so 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = +2.7v to +3.6v (max1240); v dd = +2.7v to +5.25v (max1241); 73ksps, f s clk = 2.1mhz (50% duty cycle); max1240?.7? capacitor at ref pin, max1241?xternal reference; v ref = 2.500v applied to ref pin; t a = t min to t max ; unless otherwise noted.) note 1: tested at v dd = +2.7v. note 2: relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offset have been calibrated. note 3: max1240?nternal reference, offset nulled; max1241?xternal reference (v ref = +2.500v), offset nulled. note 4: external load should not change during conversion for specified accuracy. note 5: guaranteed by design. not subject to production testing. note 6: measured as [v fs (2.7v) - v fs (v dd(max )]. note 7: to guarantee acquisition time, t acq is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired. sclk pulse width low t cl 200 ns sclk pulse width high t ch 200 ns sclk clock frequency f sclk 0 2.1 mhz cs rise to output disable t tr 240 ns sclk low to cs fall setup time t cs0 50 ns dout rise to sclk rise (note 5) t str 0 ns cs pulse width t cs 240 ns figure 2, c load = 50pf cs fall to output enable t dv 240 ns figure 1, c load = 50pf parameters symbol min typ max units conditions acquisition time t acq 1.5 ? cs = v dd (note 6) timing characteristics (figure 8) (v dd = +2.7v to +3.6v (max1240); v dd = +2.7v to +5.25v (max1241); t a = t min to t max , unless otherwise noted.) parameters symbol min typ max units conditions 2.7 3.6 max1240 2.7 5.25 max1241 v dd supply voltage v ?.3 (note 5) psr supply rejection mv 20 240 sclk fall to output data valid t do 20 200 ns figure 1, c load = 50pf max124_ _c/e max124_ _m 1.4 2.0 operating mode 1.6 2.5 v dd = 3.6v 3.5 15 v dd = 5.25v v dd = 3.6v v dd = 5.25v i dd 1.9 10 power-down, digital inputs at 0v or v dd 1.4 3.5 ? 0.9 1.5 v dd = 3.6v max1240c max1241a/b supply current max1240a/b ma 1.6 3.8 v dd = 3.6v v dd = 5.25v 0.9 2.8 max1241c power requirements
max1240/max1241 +2.7v, low-power, 12-bit serial adcs in 8-pin so _______________________________________________________________________________________ 5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 2.25 2.75 3.25 3.75 4.25 4.75 5.25 offset error vs. supply voltage max1241-03 supply voltage (v) offset error (lsb) __________________________________________typical operating characteristics (v dd = 3.0v, v ref = 2.5v, f sclk = 2.1mhz, c l = 20pf, t a = +25?, unless otherwise noted.) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 24 356 operating supply current vs. supply voltage max1241-d supply voltage (v) operating supply current (ma) r l = code = 101010100000 max1241 max1240 0.8 0.9 1.0 1.1 1.2 1.3 -60 -20 20 60 100 140 supply current vs. temperature temperature (?) supply current (ma) max1241-a/new max1241 max1240 r load = code = 10101010000 dout dout 6k dgnd c load = 50pf c load = 50pf 6k dgnd +2.7v b) high-z to v ol and v oh to v ol a) high-z to v oh and v ol to v oh figure 1. load circuits for dout enable time dout dout 6k dgnd c load = 50pf c load = 50pf 6k dgnd +2.7v b) v ol to high-z a) v oh to high-z figure 2. load circuits for dout disable time
2.494 2.495 2.496 2.497 2.498 2.499 2.500 2.501 -60 -20 20 60 100 140 max1240 internal reference voltage vs. temperature temperature (?) vref (v) max1241-0y v dd = 2.7v v dd = 3.6v 0 0.4 0.2 0.8 0.6 1.0 1.2 2.25 3.25 3.75 2.75 4.25 4.75 5.25 integral nonlinearity vs. supply voltage max1241-09/new supply voltage (v) inl (lsb) max1240 max1241 max1240/max1241 +2.7v, low-power, 12-bit serial adcs in 8-pin so 6 _______________________________________________________________________________________ ____________________________typical operating characteristics (continued) (v dd = 3.0v, v ref = 2.5v, f sclk = 2.1mhz, c l = 20pf, t a = +25?, unless otherwise noted.) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 2.25 2.75 3.25 3.75 4.25 4.75 5.25 gain error vs. supply voltage max1241-07 supply voltage (v) gain error (lsb) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 -55 -30 -5 20 45 70 145 120 95 gain error vs. temperature max1241-08 temperature (?) gain error (lsb) v dd = 2.7v 2.5020 2.4990 2.25 2.75 max1240 internal reference voltage vs. supply voltage 2.5015 2.5005 2.5010 2.5000 2.4995 v dd (v) vref (v) 3.75 5.25 3.25 4.25 4.75 max1241-0x 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -60 -20 20 60 100 140 shutdown supply current vs. temperature max1241-b temperature (?) shutdown supply current ( a) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 -55 -30 -5 20 45 70 95 120 145 offset error vs. temperature max1241-06 temperature (?) offset error (lsb) v dd = 2.7v 4.0 3.5 0 2.25 2.75 shutdown supply current vs. supply voltage 3.0 2.5 1.5 2.0 1.0 0.5 supply voltage (v) shutdown supply current ( a) 3.75 5.25 3.25 4.25 4.75 max1241-c/new 0 0.6 0.4 0.2 0.8 1.0 1.2 -60 20 0 -40 -20 40 60 80 100 120 140 integral nonlinearity vs. temperature max1241-10/new temperature (?) inl (lsb) v dd = 2.7v max1240 max1241
max1240/max1241 +2.7v, low-power, 12-bit serial adcs in 8-pin so _______________________________________________________________________________________ 7 _______________________________________________________________________ pin description 6 dout serial data output. data changes state at sclk? falling edge. dout is high impedance when cs is high. 8 sclk 3 shdn three-level shutdown input. pulling shdn low shuts the max1240/max1241 down to 15? (max) supply current. both the max1240 and max1241 are fully operational with either shdn high or unconnected. for the max1240, pulling shdn high enables the internal reference, and letting shdn open disables the internal reference and allows for the use of an external reference. 4 ref reference voltage for analog-to-digital conversion. internal 2.5v reference output for max1240; bypass with 4.7? capacitor. external reference voltage input for max1241, or for max1240 with the internal reference disabled. bypass ref with a minimum of 0.1? when using an external reference. 7 cs active-low chip select initiates conversions on the falling edge. when cs is high, dout is high impedance. 5 gnd analog and digital ground 2 ain sampling analog input, 0v to v ref range name function 1 v dd positive supply voltage: 2.7v to 3.6v, (max1240); 2.7v to 5.25v (max1241) pin serial clock input. sclk clocks data out at rates up to 2.1mhz. 0.6 integral nonlinearity vs. code -0.6 0 -0.2 -0.4 0.4 0.2 max1241-11a/new inl (lsb) code 1024 2048 3072 4096 0 20 -140 0 37.50 fft plot -120 0 -80 -100 -40 -20 -60 18.75 amplitude (db) frequency (khz) f ain = 10khz, 2.5v p-p f sample = 73ksps max1241-toc12a ____________________________typical operating characteristics (continued) (v dd = 3.0v, ref = 2.5v, f sclk = 2.1mhz, c l = 20pf, t a = +25?, unless otherwise noted.)
max1240/max1241 +2.7v, low-power, 12-bit serial adcs in 8-pin so 8 _______________________________________________________________________________________ _______________detailed description converter operation the max1240/max1241 use an input track/hold (t/h) and successive-approximation register (sar) circuitry to convert an analog input signal to a digital 12-bit out- put. no external-hold capacitor is needed for the t/h. figure 3 shows the max1240/max1241 in its simplest configuration. the max1240/max1241 convert input signals in the 0v to v ref range in 9?, including t/h acquisition time. the max1240? internal reference is trimmed to 2.5v, while the max1241 requires an external reference. both devices accept voltages from 1.0v to v dd . the serial interface requires only three digital lines (sclk, cs , and dout) and provides an easy interface to microprocessors (?s). the max1240/max1241 have two modes: normal and shutdown. pulling shdn low shuts the device down and reduces supply current below 10? (v dd 3.6v ) , while pulling shdn high or leaving it open puts the device into operational mode. pulling cs low initiates a conver- sion. the conversion result is available at dout in unipolar serial format. the serial data stream consists of a high bit, signaling the end of conversion (eoc), fol- lowed by the data bits (msb first). analog input figure 4 illustrates the sampling architecture of the ana- log-to-digital converter? (adc?) comparator. the full- scale input voltage is set by the voltage at ref. track/hold in track mode, the analog signal is acquired and stored in the internal hold capacitor. in hold mode, the t/h switch opens and maintains a constant input to the adc? sar section. during acquisition, the analog input (ain) charges capacitor c hold . bringing cs low ends the acquisition interval. at this instant, the t/h switches the input side of c hold to gnd. the retained charge on c hold repre- sents a sample of the input, unbalancing node zero at the comparator? input. in hold mode, the capacitive digital-to-analog converter (dac) adjusts during the remainder of the conversion cycle to restore node zero to 0v within the limits of 12- bit resolution. this action is equivalent to transferring a charge from c hold to the binary-weighted capacitive dac, which in turn forms a digital representation of the analog input signal. at the conversion? end, the input side of c hold switches back to ain, and c hold charges to the input signal again. the time required for the t/h to acquire an input signal is a function of how quickly its input capacitance is charged. if the input signal? source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. the acquisition time (t acq ) is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired. acquisition time is calculated by: t acq = 9(r s + r in ) x 16pf where r in = 9k , r s = the input signal? source imped- ance, and t acq is never less than 1.5?. source imped- ances below 1k do not significantly affect the adc? ac performance. higher source impedances can be used if a 0.01? capacitor is connected to the analog input. note that the input capacitor forms an rc filter with the input source impedance, limiting the adc? input signal bandwidth. ain track input hold gnd track hold 9k r in c hold 16pf -+ c switch comparator zero ref 12-bit capacitive dac at the sampling instant, the input switches from ain to gnd. shutdown input analog input 0v to v ref +2.7v to +3.6v* * ** v dd,max = +5.25v (max1241) 4.7 f (max1240) 0.1 f (max1241) 1 2 3 4 v dd ain shdn ref 8 7 6 5 sclk cs dout gnd serial interface c** 4.7 f 0.1 f reference input (max1241 only) max1240 max1241 figure 3. operational diagram figure 4. equivalent input circuit
max1240/max1241 +2.7v, low-power, 12-bit serial adcs in 8-pin so _______________________________________________________________________________________ 9 input bandwidth the adcs?input tracking circuitry has a 2.25mhz small- signal bandwidth, so it is possible to digitize high- speed transient events and measure periodic signals with bandwidths exceeding the adc? sampling rate by using undersampling techniques. to avoid aliasing of unwanted high-frequency signals into the frequency band of interest, anti-alias filtering is recommended. analog input protection internal protection diodes, which clamp the analog input to v dd and gnd, allow the input to swing from gnd - 0.3v to v dd + 0.3v without damage. however, for accurate conversions near full scale, the input must not exceed v dd by more than 50mv, or be lower than gnd by 50mv. if the analog input exceeds 50mv beyond the sup- plies, limit the input current to 2ma. internal reference (max1240) the max1240 has an on-chip voltage reference trimmed to 2.5v. the internal reference output is con- nected to ref and also drives the internal capacitive dac. the output can be used as a reference voltage source for other components and can source up to 400?. bypass ref with a 4.7? capacitor. larger capacitors increase wake-up time when exiting shut- down (see the section using shdn to reduce supply current ). the internal reference is enabled by pulling the shdn pin high. letting shdn open disables the internal reference, which allows the use of an external reference, as described in the external reference section. external reference the max1240/max1241 operate with an external refer- ence at the ref pin. to use the max1240 with an external reference, disable the internal reference by let- ting shdn open. stay within the +1.0v to v dd voltage range to achieve specified accuracy. the minimum input impedance is 18k for dc currents. during con- version, the external reference must be able to deliver up to 250? of dc load current and have an output impedance of 10 or less. the recommended mini- mum value for the bypass capacitor is 0.1?. if the ref- erence has higher output impedance or is noisy, bypass it close to the ref pin with a 4.7? capacitor. ____________________serial interface initialization after power-up and starting a conversion when power is first applied, and if shdn is not pulled low, it takes the fully discharged 4.7? reference bypass capacitor up to 20ms to provide adequate charge for specified accuracy. with an external refer- ence, the internal reset time is 10? after the power supplies have stabilized. no conversions should be performed during these times. to start a conversion, pull cs low. at cs ? falling edge, the t/h enters its hold mode and a conversion is initiat- ed. after an internally timed conversion period, the end of conversion is signaled by dout pulling high. data can then be shifted out serially with the external clock. complete conversion sequence t wake powered up powered down powered up conversion 0 conversion 1 dout cs shdn figure 5. shutdown sequence
max1240/max1241 +2.7v, low-power, 12-bit serial adcs in 8-pin so 10 ______________________________________________________________________________________ using shdn to reduce supply current power consumption can be reduced significantly by shutting down the max1240/max1241 between con- versions. figure 6 shows a plot of average supply cur- rent versus conversion rate. because the max1241 uses an external reference voltage (assumed to be pre- sent continuously), it ?akes up?from shutdown more quickly (in 4?) and therefore provides lower average supply currents. the wake-up time (t wake ) is the time from when shdn is deasserted to the time when a con- version may be initiated (figure 5). for the max1240, this time depends on the time in shutdown (figure 7) because the external 4.7? reference bypass capacitor loses charge slowly during shutdown. external clock the actual conversion does not require the external clock. this allows the conversion result to be read back at the ?? convenience at any clock rate from up to 2.1mhz. the clock duty cycle is unrestricted if each clock phase is at least 200ns. do not run the clock while a conversion is in progress. timing and control conversion-start and data-read operations are controlled by the cs and sclk digital inputs. the timing diagrams of figures 8 and 9 outline serial-interface operation. a cs falling edge initiates a conversion sequence: the t/h stage holds the input voltage, the adc begins to convert, and dout changes from high impedance to logic low. sclk must be kept low during the conver- sion. an internal register stores the data when the con- version is in progress. 10 1 0.01 0.001 0.1 1 10 100 1k 10k 100k 0.1 conversion rate (hz) supply currnet (ma) v dd = v ref = 3.0v r load = , c load = 50pf code = 010101010000 max1241 fig. 06a max1241 max1240 figure 6. average supply current vs. conversion rate 1.0 0.0 0.001 0.01 0.1 1 10 0.8 0.6 0.4 0.2 time in shutdown (sec) power-up delay (ms) max1240/41-07a figure 7. typical reference power-up delay vs. time in shutdown eoc interface idle conversion in progress eoc 0 s trailing zeros idle clock out serial data track/hold state track hold track dout b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 sclk 14 8 12 16 7.5 s (t conv ) hold 0 s (t cs ) total = 13.7 s 12.5 0.476 s = 5.95 s cycle time cs 0.24 s figure 8. interface timing sequence
end of conversion (eoc) is signaled by dout going high. dout? rising edge can be used as a framing signal. sclk shifts the data out of this register any time after the conversion is complete. dout transitions on sclk? falling edge. the next falling clock edge pro- duces the msb of the conversion at dout, followed by the remaining bits. since there are 12 data bits and one leading high bit, at least 13 falling clock edges are needed to shift out these bits. extra clock pulses occur- ring after the conversion result has been clocked out, and prior to a rising edge of cs , produce trailing zeros at dout and have no effect on converter operation. minimum cycle time is accomplished by using dout? rising edge as the eoc signal. clock out the data with 12.5 clock cycles at full speed. pull cs high after reading the conversion? lsb. after the specified minimum time (t cs ), cs can be pulled low again to initiate the next conversion. output coding and transfer function the data output from the max1240/max1241 is binary, and figure 10 depicts the nominal transfer function. code transitions occur halfway between successive- integer lsb values. if v ref = +2.500v, then 1 lsb = 610? or 2.500v/4096. ____________ applications information connection to standard interfaces the max1240/max1241 serial interface is fully compat- ible with spi/qspi and microwire standard serial interfaces (figure 11). if a serial interface is available, set the cpu? serial interface in master mode so the cpu generates the ser- ial clock. choose a clock frequency up to 2.1mhz. 1) use a general-purpose i/o line on the cpu to pull cs low. keep sclk low. 2) wait the for the maximum conversion time specified before activating sclk. alternatively, look for a dout rising edge to determine the end of conversion. 3) activate sclk for a minimum of 13 clock cycles. the first falling clock edge produces the msb of the dout conversion. dout output data transitions on sclk? falling edge and is available in msb-first for- mat. observe the sclk to dout valid timing char- acteristic. data can be clocked into the ? on sclk? rising edge. 4) pull cs high at or after the 13th falling clock edge. if cs remains low, trailing zeros are clocked out after the lsb. max1240/max1241 +2.7v, low-power, 12-bit serial adcs in 8-pin so ______________________________________________________________________________________ 11 11 111 11 110 11 101 00 011 00 010 00 001 00 000 012 fs output code fs - 3/2 lsb input voltage (lsbs) fs = v ref - 1 lsb 1 lsb = v ref 4096 full-scale transition 3 cs sclk dout internal t/h (track/acquire) t cs0 t conv t dv t apr t str (hold) (track/acquire) b2 b1 b0 t ch t do t cl t tr t cs figure 10. unipolar transfer function, full scale (fs) = v ref - 1 lsb, zero scale (zs) = gnd figure 9. detailed serial-interface timing
max1240/max1241 +2.7v, low-power, 12-bit serial adcs in 8-pin so 12 ______________________________________________________________________________________ 5) with cs = high, wait the minimum specified time, t cs , before initiating a new conversion by pulling cs low. if a conversion is aborted by pulling cs high before the conversion? end, wait for the minimum acquisi- tion time, t acq , before starting a new conversion. cs must be held low until all data bits are clocked out. data can be output in two bytes or continuously, as shown in figure 8. the bytes contain the result of the conversion padded with one leading 1, and trailing 0s. spi and microwire when using spi or microwire, set cpol = 0 and cpha = 0. conversion begins with a cs falling edge. dout goes low, indicating a conversion in progress. wait until dout goes high or until the maximum specified 7.5? conversion time elapses. two consecutive 1-byte reads are required to get the full 12 bits from the adc. dout output data transitions on sclk? falling edge and is clocked into the ? on sclk? rising edge. the first byte contains a leading 1, and seven bits of con- version result. the second byte contains the remaining five bits and three trailing zeros. see figure 11 for con- nections and figure 12 for timing. qspi set cpol = cpha = 0. unlike spi, which requires two 1-byte reads to acquire the 12 bits of data from the adc, qspi allows the minimum number of clock cycles neces- sary to clock in the data. the max1240/max1241 requires 13 clock cycles from the ? to clock out the 12 bits of data with no trailing zeros (figure 13). the maxi- mum clock frequency to ensure compatibility with qspi is 2.097mhz. layout, grounding, and bypassing for best performance, use printed circuit boards. wire- wrap boards are not recommended. board layout should ensure that digital and analog signal lines are separated from each other. do not run analog and digital (especially clock) lines parallel to one another, or digital lines under- neath the adc package. figure 14 shows the recommended system ground con- nections. establish a single-point analog ground (?tar ground point) at gnd, separate from the logic ground. connect all other analog grounds and dgnd to this star ground point for further noise reduction. no other digital system ground should be connected to this single-point analog ground. the ground return to the power supply for this ground should be low impedance and as short as possible for noise-free operation. high-frequency noise in the v dd power supply may affect the adc? high-speed comparator. bypass this supply to the single-point analog ground with 0.1? and 4.7? bypass capacitors. minimize capacitor lead lengths for best supply-noise rejection. if the power supply is very noisy, a 10 resistor can be connected as a lowpass filter to attenuate supply noise (figure 14). cs sclk dout i/o sck miso +3v ss a) spi cs sclk dout cs sck miso +3v ss b) qspi max1240 max1241 max1240 max1241 max1240 max1241 cs sclk dout i/o sk si c) microwire figure 11. common serial-interface connections to the max1241
max1240/max1241 +2.7v, low-power, 12-bit serial adcs in 8-pin so ______________________________________________________________________________________ 13 high-z d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t conv dout* cs sclk 1st byte read 2nd byte read eoc msb lsb *when cs is high, dout = high -z d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t conv dout* cs sclk eoc msb lsb high-z *when cs is high, dout = high -z figure 12. spi/microwire serial interface timing (cpol = cpha = 0) figure 13. qspi serial interface timing (cpol = cpha = 0) supplies +3v +3v gnd dgnd +3v digital circuitry gnd v dd max1240 max1241 *optional r* = 10 4.7 f 0.1 f figure 14. power-supply grounding condition
max1240/max1241 +2.7v, low-power, 12-bit serial adcs in 8-pin so 14 ______________________________________________________________________________________ part max1240aepa+ max1240besa+ max1240bmja+ -55? to +125? -40? to +85? -40? to +85? temp range pin- package 8 pdip 8 so 8 cerdip ? MAX1241AEPA+ -40? to +85? 8 pdip 1 / 2 max1241bepa+ -40? to +85? 8 pdip ? max1241aesa+ -40? to +85? 8 so 1 / 2 max1241besa+ -40? to +85? 8 so inl (lsb) 1 / 2 ? ? ? max1241amja+ -55? to +125? 8 cerdip ? 1 / 2 max1241bmja+ -55? to +125? 8 cerdip ? ? max1240amja+ -55? to +125? 8 cerdip ? 1 / 2 max1241bc/d 0? to +70? dice* ? + denotes lead(pb)-free/rohs-compliant package. * dice are specified at t a = +25?, dc parameters only. ? contact factory for availability and processing to mil-std-883. __ordering information (continued) chip information process: bicmos substrate connected to gnd max1241 acpa+ max1241bcpa+ max1241bcsa + 0? to +70? 0? to +70? 0? to +70? 8 pdip 8 pdip 8 so 1 / 2 ? ? max1241acsa+ 0? to +70? 8 so 1 / 2 max1240aesa+ -40? to +85? 8 so 1 / 2 max1240bepa+ -40? to +85? 8 pdip ? max1240cepa+ -40? to +85? 8 pdip ? max1240cesa+ -40? to +85? 8 so ? max1240cmja+ -55? to +125? 8 cerdip ? ? max1241ccpa+ 0? to +70? 8 pdip ? max1241ccsa+ 0? to +70? 8 so ? max1241cepa+ -40? to +85? 8 pdip ? max1241cesa+ -40? to +85? 8 so ? max1241cmja+ -55? to +125? 8 cerdip ? ? package information package type package code outline no. land pattern no. 8 pdip p8+2 21-0043 8 so s8+5 21-0041 90-0096 8 cerdip j8+2 21-0045 for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a dif- ferent suffix character, but the drawing pertains to the package regardless of rohs status.
max1240/max1241 2.7v, low-power, 12-bit serial adcs in 8-pin so maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 15 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 3 3/10 added automotive grade to data sheet 1, 2, 3, 7, 9, 14, 15, 16 4 6/10 future product note removed from one part in the ordering information 1 5 8/10 removed max1240bc/d and add max1240cc/d 1

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